Virtual Signal Spy...Debugging Made easy

If you are using Questasim, your waveform debugging will be easy if start using Virtual Signal Option. With the help of this option New Signals can be created by applying the expressions on the Existing signals. You can also delay the signals by certain amount when comparing input with output which will be general case many times.

Few examples include:

Create a virtual signal that is the same as /top/signalA except it is delayed by 10 ps. 

  virtual signal -delay {10 ps} {/top/signalA} myDelayedSignalA

Create a three-bit signal, chip.address_mode, as an alias to the specified bits. 

  virtual signal { chip.instruction[23:21] } address_mode

Create a two-bit signal (with an enumerated type) based on the results of the subexpressions. For example, if aold equals anew, then the first bit is true (1). Alternatively, if bold does not equal bnew, the second bit is false (0). Each subexpression is evaluated independently.

  virtual signal {(aold == anew) & (bold == bnew)} myequalityvector

Create signal newbus that is a concatenation of bus1 (bit-reversed) and bus2[7:4] (bit- reversed). Assuming bus1 has indices running 7 downto 0, the result will be newbus[11:0] with the upper 8 bits being bus1[0:7] and the lower 4 bits being bus2[4:7]. 

  virtual signal {(concat_reverse)(bus1 & bus2[7:4])} newbus

I personally felt this option saves lot of time and effort during debugging.

Hope the same for you too...