Using the UVM 1.0 Release with Questa « Verification Horizons BLOG

Using the UVM 1.0 Release with Questa « Verification Horizons BLOG

Comparing Signal Strength in Verilog/Systemverilog

Language doesn’t allow you directly to compare the signal strength. But you can compare strengths by converting the strings. By using the following macro you can achieve the required function.

`define compSigValues(siga, sigb)
  begin
  string sigaStr, sigbStr;
  $sformat(sigaStr, "%v", siga);
  $sformat(sigbStr, "%v", sigb);
  if ( sigaStr == sigbStr )
$display("Signal values %s and %s match", sigaStr, sigbStr);
  else
$display("Signal values %s and %s don't match", sigaStr, sigbStr);
 end

Escaped Identifiers in hierarchical Path usage in Verilog/Systemverilog

An identifier in Verilog and SystemVerilog is the name of some object, such as the name of a module, the name of a wire, the name of a variable, or the name of a function. The legal characters in an identifier are alphabetic characters, numbers, underscore or dollar sign. All other characters, such as +, -, (, ), [ and ], are illegal in an identifier name.
Verilog and SystemVerilog allow these illegal characters to be used in a name by escaping the identifier. A name is escaped by preceding the name with a back slash ( \ ) and terminating the name with a white space character.


module \d-flop (output q, \q~ , input \d[0] ,clk, \rst- ); 
...
endmodule


Note in the above example that a white space character must be used before the commas that separate an escaped identifier from the next item in the list. A white space is also required between the last escaped name, \reset-, and the closing parenthesis.
The gotcha is when an escaped identifier is used as part of a hierarchy path. The escaped identifier must be terminated by a white space. That white space looks like it breaks the hierarchy path into two identifiers, but the terminating white space is ignored, which, in effect, concatenates the two names into one name.


The following examples illustrate the use of white space after references to escaped identifiers. Module chip uses named port connections to escaped port names identifiers. The $display contains a relative hierarchy path that contains an escaped identifier.


module chip (output [7:0] q, input [7:0] d, input clk, rstN); 
\d-flop \d-0 (.q(q[0]), .\q~ (), .\d[0] (d[0]), .clk(clk), .\rst- (rstN));
initial 
begin 
$display(“d = %b”, \d-0.\d[0] );    // Error - As White Space is missing
$display(“d = %b”, \d-0 .\d[0] );   // Correct Usage as White Space is used.
end
endmodule


The Netlist file normally will be using Escaped Identifiers to preserve the hierarchical path of design.

Parameterized Classes, Static Members and the Factory Macros « Verification Horizons BLOG

Good Post on OVM Parameterized Macros

Parameterized Classes, Static Members and the Factory Macros « Verification Horizons BLOG: "and the Factory Macro"

Adding Validation support to OVM Agents

OVM Agents need to be developed to support the Validation activity also. Sometimes during validation we will be having requirement to provide the Packets or input data in file format. If OVM Agents has the capability to dump the packet into file at various abstraction levels, that file can be used as Input during validation. Adding this logic may not be overhead to Agent when compared against the advantages.