Implicit Net Declartions in Verilog and Systemverilog

Implicit net declarations

Gotcha: Mis-typed identifiers may infer an implicit net instead of a syntax error

What does a compiler do when it encounters an undeclared identifier? The answer to this

question depends on the context in which the undeclared identifier is used.

·         If an undeclared identifier is used on the right or left-hand side of a procedural assignment, then a compilation or elaboration error occurs.

·         If an undeclared identifier is used on the right-hand side of a continuous assignment, then a compilation or elaboration error occurs.

·         If an undeclared identifier is used on the left-hand side of a continuous assignment, then animplicit net declaration is inferred, and no error or warning is reported.

·         If an undeclared identifier is used as a connection to an instance of a module, interface, program, or primitive, then an implicit net is inferred, and no error or warning is reported.

The last two rules above are gotchas, as is illustrated in the following example:

module bad_adder (input wire a, b, ci,

output wire sum, co);

wire n1, n2, n3;

xor g1 (n1, a, b);

xor g2 (sum, nl, ci); // GOTCHA!

and g3 (n2, a, b, c); // GOTCHA!

and g4 (n3, n1, ci);

or g5 (co, n2, n3);

endmodule

One gotcha in this example is the declaration of n1 (“en-one”) but the usage of nl (“en-ell”) in the g2 primitive instance. Another gotcha is an extra identifier, c, in the second g3 primitive instance. These typos are not syntax errors. Instead, they infer implicit nets in the design, causing

functional errors that must be detected and debugged. GOTCHA! This example comes from a debugging lab in Sutherland HDL’s Verilog training course (but

without the GOTCHA comments). It is surprising how difficult the two typos in the netlist can be to find. Imagine how much more difficult a simple typo would be to find in a one-million gate netlist with several layers of design hierarchy. Why does Verilog allow this gotcha? Because, like many gotchas, the ability to have implicit data types automatically inferred can be useful, when not abused. One of the benefits of implicit data types is that in a large, multi-million gate design

that has thousands of interconnecting wires, it is not necessary to explicitly declare every wire. How to avoid this gotcha: There are two ways to avoid this implicit data type gotcha. Verilog provides a ‘default_nettype none compiler directive. When this directive is set, implicit data types are disabled, which will make any undeclared signal name a syntax error. A limitation of this directive is that the benefits of implicit data types are also lost. Another limitation is that

compiler directives are not bound by design blocks, or even by source code files. If the ‘default_nettype none directive is turned on in one file, it can affect the compilation of other files, which is yet another GOTCHA!. To avoid this gotcha, the directive ‘default_nettype wire should be added at the end of each file where implicit nets have been turned off.

‘default_nettype none // turn off implicit data types

module adder (input wire a, b, ci,

output wire sum, co);

wire n1, n2, n3;

xor g1 (n1, a, b);

xor g2 (sum, nl, ci); // ERROR! nl is not declared

and g3 (n2, a, b, c); // ERROR! c is not declared

and g4 (n3, n1, ci);

or g5 (co, n2, n3);

endmodule

‘default_nettype wire // turn implicit nets on again to avoid side-effects

SystemVerilog provides two convenient short cuts for connecting nets to module instances, . and .*. These shortcuts remove the repetition in Verilog named port connections. By reducing the number of times a signal name must be typed, the possibility of typographical errors is also reduced. The . and .* shortcuts also require that all nets be explicitly declared. The shortcuts will not infer an implicit data type due to a typo. Another advantage of these SystemVerilog shortcuts is that they are local to the module in which they are used. The shortcuts do not affect other design blocks, the way compiler directives can.

module adder (input wire a, b, ci,

output wire sum, co);

...

Endmodule

module top;

wire a, b, ci;

wire s1, s2, s3, c1, c2, c3;

adder i1 (.a(a), .b(b), .ci(ci), .sum(s1), .co(c1) ); // Verilog style

adder i2 (.a, .b, .ci, .sum(s2), .co(c2) ); // SystemVerilog .name style

adder i3 (.*, .sum(s3), .co(c3) ); // SystemVerilog .* style

endmodule